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IPU MCA Semester 1 - Computer Organization (End Term Paper 2015-2016)

First Semester - MCA
Paper Code: MCA - 107

Subject: Computer Organization

IPU MCA Semester 1 - Computer Organization (End Term Paper 2015-2016)

Time: 3 Hours Maximum Marks: 75

Note: Attempt any five questions including QNo. 1 which is compulsory

Question 1: (2.5 × 10 = 25)

Which register keeps track of the instruction stored in program stored in memory?
What is CSA?
Differentiate between a level triggered from an edge triggered flip-flop.
Which addressing mode is used in an instruction of the form ADD R1 and R2?
Distinguish between Array processing and Vector processing?
What are hazards?
What is opcode?
Which kind of instruction changes the flow of program?
State hierarchy of memory of computer system.
Suggest a solution to overcome the limitation on the speed of an adder.

Question 2: (6.25 × 2 = 12.5)

(a) Explain the operation of a JK master flip flop.
(b) Illustrate the working of a 4-bit bi-directional shift register.

Question 3: (6.25 × 2 = 12.5)

(a) Write a note on register transfer language.
(b) Design a 4-bit combinational circuit decrementer using four full adder circuits.

Question 4: Define the following: (12.5)

(a) micro-operation
(b) micro-instruction
(c) micro-program
(d) microcode

Question 5: (6.25 × 2 = 12.5)

(a) Show a circuit arrangement, whereby several devices may interrupt a processor on a single interrupt request line.

(b) Discuss various instruction formats.

Question 6: (6.25 × 2 = 12.5)

(a) Draw a space time diagram for a six segment pipeline showing the time it takes to process eight tasks.

(b) Distinguish between scalar RISC and superscalar RISC in terms of instruction issue, pipeline architecture and processor performance.

Question 7: (6.25 × 2 = 12.5)

(a) Explain with example the various modes of data transfer.

(b) What is the difference between isolated I/O and memory mapped I/O? State the advantages and disadvantages of each.

Question 8: (6.25 × 2 = 12.5)

(a) How many 128×8 RAM chips to provide a memory capacity of 2KB? How many address lines be required to access 2KB memory? How many lines must be decoded for chip select? Specify the size of decoders.

(b) Design an 8×8 Omega Network.

Question 9: (6.25 × 2 = 12.5)
Explain the following terms associated with cache design.

(a) Write through vs Write Back caches
(b) Cachable vs Non-Cachable data