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IPU MCA Semester 1 - Computer Organisation (End Term Question Paper 2015)



(MCA 107)
IPU MCA Semester 1 - Computer Organisation (End Term Question Paper 2015)

Question 1:

(a) Which register keeps track of the instruction stored in program stored in Memory?

(b) What is CSA?

(c) Differentiate a level triggered from a edge triggered flip-flop.

(d) Which addressing mode used in an instruction of the form ADD R1 R2?

(e) Distinguish between Array processing  and Vector processing.

(f) What are Hazards?

(g) What is opcode?

(h) Which kind of instruction changes the flow of program?

(i) State hierarchy of memory of a computer system .

(j) Suggest a solution to overcome the limitation on the speed of an adder.

Question 2:

(a) Explain the operation of a JK master slave flip-flop.       (6.25)

(b) Illustrate the working of a 4-bit bi-directional shift register.       (6.25)

Question 3:

(a) Write a note on register transfer language.       (6.25)

(b) Design a 4-bit combinational circuit decrementer using four full adder circuits.     (6.25)

Question 4: Define the following: (12.5)

(a) micro-operation

(b) micro-instruction

(c) micro-program

(d) microcode

Question 5: Show a circuit arrangement, whereby several devices may interrupt a processor on a single interrupt request line.             (6.25)

(b) Discuss various instruction formats.            (6.25)

Question 6:
(a) Draw a space time diagram for a six-segment pipeline showing the time it takes to process eight tasks.                                                                                                        (6.25)

(b) Distinguish between a scaler RISC and a super scalar RISC in terms of instruction issue, pipeline architecture and processor performance. (6.25)

Question 7:

(a) Explain with example, the various modes of data transfer.            (6.25)

(b) What is difference between isolated I/O and memory mapped I/O? State the advantages and disadvantages of each. (6.25)

Question 8:

(a) How many 128×8 RAM chips to provide a memory capacity of 2kB? How may address line will be required to access the 2 KB memory? How many lines must be decoded for chip select? Specify the size of decoders. (6.25)

(b) Design an 8×8 Omega Network. (6.25)

Question 9: Explain the following terms associated with cache design. (6.25 × 2= 12.5)

(a) Write through vs Write Back Caches
(b) Cachable vs Non Cachable Data